pcs3p7303a general purpose peak emi reduction ic ?2010 scillc. all rights reserved. publication order number: november 2010 C rev. 3 pcs3p7303/d general features 1x, lvcmos peak emi reduction input frequency: 10mhz - 70mhz @ 2.5v 10mhz - 80mhz @ 3.3v output frequency: 10mhz - 70mhz @ 2.5v 10mhz - 80mhz @ 3.3v analog deviation selection modrate selection option supply voltage: 2.5v 0.2v 3.3v 0.3v 8-pin tssop, 8l 2mmx2mm wdfn(tdfn) packages the first true drop-in solution functional description pcs3p7303a is a versatile, 3.3v/2.5v peak emi reduc tion ic based on timing-safe? technology. pcs3p7303a accepts an input clock either from a crystal or fro m an external reference (ac or dc coupled to xin / clkin ) and locks on to it delivering a 1x modulated clock outp ut. pcs3p7303a has a frequency selection (fs) control t hat facilitates selecting one of the two frequency rang es within the operating frequency range. refer to the frequency selection table for details . pcs3p7303a has an ssextr pin to select different deviations depending upon the value of an external resistor connected between ssextr and gnd. modulation rate (mr) control selects two different modulation rates . pcs3p7303a operates from a 3.3v/2.5v supply and is available in an 8-pin tssop and 8l 2mmx2mm wdfn packages. application pcs3p7303a is targeted for many applications includ ing usb and sata. block diagram vdd gnd fs modout mr pll crystal oscillator xout xin / clkin ssextr
pcs3p7303a rev. 3 | page 2 of 10 | www.onsemi.com xin / clkin fs 1 2 3 4 5 6 7 8 modout ssextr vdd gnd mr pcs3p7303a xout pin configuration pin description pin # pin name pin type description 1 xin / clkin i crystal connection or external reference clock in put. 2 xout o crystal connection. if using an external reference, this pin should be left open. 3 fs i frequency select. pull low to select low frequency range. selects high frequency range when pulled high. has an internal pull-up res istor. (see frequency selection table for details.) 4 gnd p ground. 5 modout o buffered modulated clock output. 6 mr i modulation rate select. when low selects low modula tion rate. selects high modulation rate when pulled high. has an internal pull-down resistor. 7 ssextr i analog deviation selection through exter nal resistor to gnd. 8 vdd p 2.5v / 3.3v supply voltage. frequency selection table vdd (v) fs frequency (mhz) 2.5 0 10-35 1 30-70 3.3 0 10-40 1 30-80
pcs3p7303a rev. 3 | page 3 of 10 | www.onsemi.com absolute maximum rating symbol parameter rating unit vdd, v in voltage on any input pin with respect to ground -0 .5 to +4.6 v t stg storage temperature -65 to +125 c t s max. soldering temperature (10 sec) 260 c t j junction temperature 150 c t dv static discharge voltage (as per jedec std22- a114- b) 2 kv note: these are stress ratings only and are not imp lied for functional use. exposure to absolute maxim um ratings for prolonged periods of time may affect device reliability. operating conditions parameter description min max unit vdd supply voltage 2.3 3.6 v t a operating temperature (ambient temperature) -25 + 85 c c l load capacitance 10 pf c in input capacitance 7 pf dc electrical characteristics for 2.5v parameter description test conditions min typ max unit vdd supply voltage 2.3 2.5 2.7 v v il input low voltage 0.7 v v ih input high voltage 1.7 v i il input low current v in = 0v -50 a i ih input high current v in = v dd 50 a v ol output low voltage i ol = 8ma 0.6 v v oh output high voltage i oh = -8ma 1.8 v i cc static supply current xin / clkin pulled low 500 a i dd dynamic supply current unloaded output fs=0; @ 10mhz 5 ma fs=1; @ 70mhz 12 z o output impedance 45 w
pcs3p7303a rev. 3 | page 4 of 10 | www.onsemi.com switching characteristics for 2.5v parameter test conditions min typ max unit input frequency 1 / modout fs=0 10 35 mhz fs=1 30 70 duty cycle 2, 3 measured at v dd /2 45 50 55 % output rise time 2, 3 measured between 20% to 80% 1.75 2.5 ns output fall time 2,3 measured between 80% to 20% 1.0 1.6 ns cycle-to-cycle jitter 3 unloaded output fs=0 10mhz 450 600 ps 35mhz 125 250 fs=1 30mhz 225 350 70mhz 150 300 pll lock time 3 stable power supply, valid clock presented on xin / clkin 3 ms notes: 1. functionality with crystal is guaranteed by design and characterization. not 100% tested in production. 2. all parameters are specified with 10pf loaded outputs. 3. parameter is guaranteed by design and characterization. not 100% tested in production. dc electrical characteristics for 3.3v parameter description test conditions min typ max unit vdd supply voltage 3.0 3.3 3.6 v v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current v in = 0v -50 a i ih input high current v in = v dd 50 a v ol output low voltage i ol = 8ma 0.4 v v oh output high voltage i oh = -8ma 2.4 v i cc static supply current xin / clkin pulled low 700 a i dd dynamic supply current unloaded output fs=0; @ 10mhz 7 ma fs=1; @ 80mhz 20 z o output impedance 35 w
pcs3p7303a rev. 3 | page 5 of 10 | www.onsemi.com switching characteristics for 3.3v parameter test conditions min typ max unit input frequency 1 / modout fs=0 10 40 mhz fs=1 30 80 duty cycle 2, 3 measured at v dd /2 45 50 55 % output rise time 2, 3 measured between 20% to 80% 1.3 2 ns output fall time 2, 3 measured between 80% to 20% 0.9 1.3 ns cycle-to-cycle jitter 3 unloaded output fs=0 10mhz 450 600 ps 40mhz 125 250 fs=1 30mhz 225 350 80mhz 125 250 pll lock time 3 stable power supply, valid clock presented on xin / clkin 3 ms notes: 1. functionality with crystal is guaranteed by design and characterization. not 100% tested in production. 2. all parameters are specified with10pf loaded o utputs. 3. parameter is guaranteed by design and characterization. not 100% tested in production. typical crystal specifications fundamental at cut parallel resonant crystal nominal frequency 25mhz frequency tolerance 50ppm or better at 25c operating temperature range -25c to +85c storage temperature -40c to +85c load capacitance(c p ) 18pf shunt capacitance 7pf maximum esr 25 w note: c l is the load capacitance and r1 is used to prevent oscillations at overtone frequency of the fundament al frequency. typical crystal interface circuit c l = 2*(c p C c s ), where c p = load capacitance of crystal from crystal vendor datasheet. c s = stray capacitance due to c in, pcb, trace, etc. xout xin / clkin pcs3p730 3 a r1 c l c l crystal r
pcs3p7303a rev. 3 | page 6 of 10 | www.onsemi.com switching waveforms duty cycle timing output rise/fall time application schematic t 3 output t 4 20% 80% 20% 80% t 2 t 1 v dd /2 v dd /2 v dd /2 output note: fs (pin#3) mr (pin#6): connect to vdd or gnd refer to pin description table for functi onality details. analog deviation control ssextr can be pulled high to turn off deviation. xin/clkin xout ssextr modout fs gnd 1 2 3 4 5 7 8 vdd mr 6 vdd 0 0 clkin 0 vdd 0 r external deviation control 0.1uf r c vdd noise reduction filter
pcs3p7303a rev. 3 | page 7 of 10 | www.onsemi.com charts deviation vs resistance (fs=0, mr=0) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 20 40 60 80 100 120 140 160 180 200 220 240 resistance (k ) d ev iation(% ) 12m 27m 33m deviation vs resistance (fs=1, mr=0) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 20 40 60 80 100 120 140 160 180 200 220 240 resistance (k ) d ev iation(% ) 33m 40m 50m deviation vs resistance (fs=0, mr=1) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 20 40 60 80 100 120 140 160 180 200 220 240 resistance (k ) d ev iation(% ) 12m 27m 33m deviation vs resistance (fs=1, mr=1) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 20 40 60 80 100 120 140 160 180 200 220 240 resistance (k ) d ev iation(% ) 33m 40m 50m note: device to device variation of deviation is 10% ( 0c to +70c) and 25% (-25c to +85c)
pcs3p7303a rev. 3 | page 8 of 10 | www.onsemi.com e h a a1 a2 d b c l q e package information 8-lead tssop package (4.40-mm body) symbol dimensions inches millimeters min max min max a 0.043 1.10 a1 0.002 0.006 0.05 0.15 a2 0.033 0.037 0.85 0.95 b 0.008 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 d 0.114 0.122 2.90 3.10 e 0.169 0.177 4.30 4.50 e 0.026 bsc 0.65 bsc h 0.252 bsc 6.40 bsc l 0.020 0.028 0.50 0.70 0 8 0 8
pcs3p7303a rev. 3 | page 9 of 10 | www.onsemi.com 8l 2mmx2mm wdfn package outline drawing symbol dimensions inches millimeters min max min max a 0.027 0.0315 0.70 0.80 a3 0.008 bsc 0.203 bsc b 0.008 0.012 0.20 0.30 d 0.079 bsc 2.00 bsc e 0.078 bsc 2.00 bsc e 0.020 bsc 0.50 bsc l 0.020 0.024 0.50 0.60
pcs3p7303a note: many on semiconductor products are protected by issued patents or applications for patent. on semiconductor and are registered trademarks of semiconductor componen ts industries, llc (scillc). scillc reserves the ri ght to make changes without further notice to any products herein. sci llc makes no warranty, representation or guarantee regarding the suitability of its products for any p articular purpose, nor does scillc assume any liability arisi ng out of the application or use of any product or circuit, and specifically disclaims any and all lia bility, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applica tions and actual performance may vary over time. al l operating parameters, including typicals must b e validated for each customer application by customer 's technical experts. scillc does not convey any l icense under its patent rights nor the rights of ot hers. scillc products are not designed, intended, or auth orized for use as components in systems intended fo r surgical implant into the body, or other applicat ions intended to support or sustain life, or for any oth er application in which the failure of the scillc p roduct could create a situation where personal inju ry or death may occur. should buyer purchase or use scillc pro ducts for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs , damages, and expenses, and reasonable attorney fe es arising out of, directly or indirectly, any claim of person al injury or death associated with such unintended or unauthorized use, even if such claim alleges tha t scillc was negligent regarding the design or manufacture o f the part. scillc is an equal opportunity/affirmat ive action employer. u.s patent pending; timing-sa fe and active bead are trademarks of pulsecore semicon ductor, a wholly owned subsidiary of on semiconduct or. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ordering code part number marking package temperature pcs3p7303ag-08tr bkl 8-pin tssop, tape and reel, gr een -25c to +85c pcs3p7303ag-08tt bkl 8-pin tssop, tube, green -25c to +85c PCS3P7303AG-08CR bk 8l wdfn (2mmx2mm), tape & reel, green -25c to +85c a microdot placed at the end of last row of marki ng or just below the last row toward the center of package indicates pb-free.
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